Revision 0.5


1.0 Introduction

RegEx is a design automation tool that generates RTL code for implementing Command and Status registers for management of any ASIC by software. Besides providing the ability to implement a variety of registers, it has the ability to generate memories and interrupt registers. Desired set of registers and memories are specified using a simple web interface and RTL code and documents that describe the registers and memories are generated with a few mouse clicks.

2.0 Structure of Generated RTL, Document and Test

The generated RTL is structured as one master module and several slave modules. The master module provides a primary interface to the CPU, address decoding and mux/demux of signals from/to the salve modules. Slave modules  implement the actual registers and memories. Each slave module typically implements a group of  registers that are used for a management of a functional block in the design.

HTML/PDF documents are generated that describe registers in the design. A simulation environment and tests are also genererated to verify generated RTL. The whole package can be downloaded in tar.gz format by by clicking on the download link.

3.0 Register Types

Following is a list of register types supported:

4.0 Memory Types

Following is the list of Memory types that can be generated:

5.0 Indirect Access

Acess type for a register or memory may be specified as an “indexed access” -- default is “direct access”. If a slave module contains registers with indexed access registers, two additional registers, index_address and index_data, are automatically created. To read or write a indexed access register, first the index of that register is written to index_address register. A subsequent read or a write to index_data register actually happens on a register whose index is currently in index_address register.

6.0 User Levels

RegEx users fall into different categories and each category has a different set priveleges as described below:

7.0 User Interface

RegEx provides web-based user interface to manage multiple projects, each of which may consist of several modules and each slave in turn may contain many registers. After login, the user can navigate to one of three primary views.

Projects View – Login will take the user to the project view from which lists current projects and provides options to select/add/modify/delete projects

Slaves View – Once a project is selected, thie view is presented. It lists all slaves in the selected project and provides options to manage slaves as well as generate, view and download RTL/document and simulation environment.

Registers View – This screen is presnented once a user selects a Slave module to manage registers in that module.

8.0 Notes