RegEx is a design automation tool that
generates RTL code for implementing Command and Status registers for
management of any ASIC by software. Besides providing the ability to
implement a variety of registers, it has the ability to generate
memories and interrupt registers. Desired set of registers and
memories are specified using a simple web interface and RTL code and
documents that describe the registers and memories are generated with
a few mouse clicks.
The generated RTL is structured as one master module and several slave modules. The master module provides a primary interface to the CPU, address decoding and mux/demux of signals from/to the salve modules. Slave modules implement the actual registers and memories. Each slave module typically implements a group of registers that are used for a management of a functional block in the design.
HTML/PDF documents are generated that
describe registers in the design. A simulation environment and
tests are also genererated to verify generated RTL. The whole package
can be downloaded in tar.gz format by by clicking on the download
Following is a list of register types supported:
RW - Read-Write -- Each field can be written to and read from
RO - Read Only -- Each field of this register can only be read and cannot be written to(writes will be ignored). Typically used for reporting the status of the functional block that is being managed. The functional block provides the value to be returned to the CPU on a read.
RO_CAR - Read Only-Clear after Read -- As above, in addition any read clears this register
RO_LATCH - Read Only-Latch -- This is also a read only register as above , but once it sees the the specified latch value from the functional block, it holds the value until the next read.
MIXED - Each field of the register can be one of the above types
INTERRUPT_WITH_MASK - Interrupt -- Interrupt register. This is also like a RO_CAR register but in addition any change in its value causes a maskable interrupt. For a register that is specified as an interrupt register, a mask register of type RW is automatically generated
INTERRUPT_WITH_ENABLE - Interrupt -- Interrupt register. This is also like a RO_CAR register but in addition any change in its value causes a maskable interrupt. For a register that is specified as an interrupt register with enable, an enable register of type RW is automatically generated
Following is the list of Memory types that can be generated:
RW - Read-Write -- Each location in memory can be written to or read from
RO - Read Only -- Each memory location can only be read and cannot be written to(writes will be ignored).
RO_CAR - Read Only-Clear after Read -- As above, in addition any read clears that location
Acess type for a register or memory may be specified as an “indexed access” -- default is “direct access”. If a slave module contains registers with indexed access registers, two additional registers, index_address and index_data, are automatically created. To read or write a indexed access register, first the index of that register is written to index_address register. A subsequent read or a write to index_data register actually happens on a register whose index is currently in index_address register.
RegEx users fall into different categories and each category has a different set priveleges as described below:
GUEST: Shared Work Space; 5 Regs/Slave; 20 total;
REGISTERED: 10 Regs/Slave; 30 total;
CUSTOMER: No limitation until license expires
RegEx provides web-based user interface to manage multiple projects, each of which may consist of several modules and each slave in turn may contain many registers. After login, the user can navigate to one of three primary views.
Projects View – Login will take the user to the project view from which lists current projects and provides options to select/add/modify/delete projects
Slaves View – Once a project is selected, thie view is presented. It lists all slaves in the selected project and provides options to manage slaves as well as generate, view and download RTL/document and simulation environment.
Registers View – This screen is presnented once a user selects a Slave module to manage registers in that module.
Memories are specified by specifying "depth" in WWW register spec as a number greater than 1. Number of locations desired is entered in this field.
Multiple copies of the same register or memory may be generated by specifying "copies" in WWW register spec form to be greater than 1.
Address and datapath widths are chosen on a per project basis
There is option to specify if a slave module will be using a slower clock(compared to the master). This information is used for selecting appropriate synchronization.
The tool is available at http://www.flowgic.com/regex.html