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Reuseability and automation are keys to bringing out successful ASIC/FPGA designs on-schedule. This is especially true with today's scale of integration and shortened design cycles. Flowgic simplifies ASIC/FPGA design process with a growing portfolio of reuseable IP cores and automation tools. Our products are designed to be efficient, flexibile, robust and above all, user-friendly. We value your input and would like to hear what you think about our products.
Take a look at our product offerings below and decide what might suit your needs. Contact us to get custom versions of these products.
Design IP Cores
Flowgic offers the following IP cores in synthesizeable Verilog. Our cores are designed with rigorous design methodology refined by years of experience -- you will have little trouble integrating the core into your design and getting a fully a functional silicon.
Interlaken Controller Family
Interlaken is a scalable chip-to-chip communication protocol defined jointly by Cisco Systems and Cortina Systems. We offer a family of Interlaken IP cores with 64, 128, 256-bit datapaths(and 2, 4, 8 lanes respectively) that operate in 10-40+ Gb/s bandwidth range.
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10 Gb/s Ethernet MAC
Flowgic's XMAC core is designed per IEEE802.3ae specification. With a simple user interface, rich feature set, and a small footprint that meets timing, this core is an ideal choice.
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Tools
RegEx
Web-based Control & Status Register/Memory Generator with ability to generate synthesizeable RTL, test environment, tests and document that is always consistent with the implementation.
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SWAT
SWAT is a bug/issue tracking tool that easy to install, maintain and use -- so easy and intuitive that it does not require or have a document aside from a README file.
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